This application claims the priority of Korean Patent Application No. 2003-31147, filed on May 16, 2003, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to an apparatus for driving a triode plasma display panel, and more particularly, to an apparatus for driving a surface discharge type triode plasma display panel in which X-electrode lines and Y-electrode lines are alternately arranged in parallel, thereby forming XY-electrode pairs, and display cells are defined in areas where the XY-electrode lines intersect address electrode lines.
2. Description of the Related Art
FIG. 1 shows the structure of a surface discharge type triode plasma display panel. FIG. 2 shows an example of a display cell of the plasma display panel shown in FIG. 1. Referring to FIGS. 1 and 2, address electrode lines AR1, AG1, . . . , AGm, ABm, dielectric layers 11 and 15, Y-electrode lines Y1, . . . , Yn, X-electrode lines X1, . . . , Xn, phosphor layers 16, partition walls 17, and a magnesium oxide (MgO) layer 12 as a protective layer are provided between front glass substrate 10 and rear glass substrate 13 of a general surface discharge plasma display panel 1.
The address electrode lines AR1 through ABm are formed on the front surface of the rear glass substrate 13 in a predetermined pattern. A rear dielectric layer 15 is formed on the entire surface of the rear glass substrate 13 having the address electrode lines AR1 through ABm. The partition walls 17 are formed on the front surface of the rear dielectric layer 15 to be parallel to the address electrode lines A1 through Am. These partition walls 17 define the discharge areas of respective display cells and serve to prevent cross talk between display cells. The phosphor layers 16 are formed between partition walls 17.
The X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn are formed on the rear surface of the front glass substrate 10 in a predetermined pattern to be orthogonal to the address electrode lines AR1 through ABm. The respective intersections define display cells. Each of the X-electrode lines X1 through Xn is composed of a transparent electrode line Xna (FIG. 2) formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode line Xnb (FIG. 2) for increasing conductivity. Each of the Y-electrode lines Y1 through Yn is composed of a transparent electrode line Yna (FIG. 2) formed of a transparent conductive material, e.g., ITO, and a metal electrode line Ynb (FIG. 2) for increasing conductivity. A front dielectric layer 11 is deposited on the entire rear surface of the front glass is substrate 10 having the rear surfaces of the X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn. The protective layer 12, e.g., a MgO layer, for protecting the panel 1 against a strong electrical field is deposited on the entire surface of the front dielectric layer 11. A gas for forming plasma is hermetically sealed in a discharge space 14.
In a driving method used by such a plasma display panel, a reset period, an address period, and a display-sustain period are sequentially performed in each subfield. In the reset period, charges in all display cells are in a uniform state. In the address period, a predetermined wall voltage is induced in selected display cells. In the display-sustain period, a predetermined alternating current voltage is applied to all of the XY-electrode line pairs so that a display-sustain discharge occurs in the selected display cells in which the predetermined wall voltage was induced during the address period. Accordingly, plasma is formed in the discharge space 14, i.e., a gas layer, of each selected display cell, and ultraviolet rays are emitted therefrom. As a result, the phosphor layer 16 is excited, thereby emitting light.
Referring to FIG. 3, a typical driving apparatus for the plasma display panel 1 shown in FIG. 1 includes a video processor 66, a logic controller 62, an address driver 63, an X-driver 64, and a Y-driver 65. The video processor 66 converts an external analog video signal into a digital signal to generate an internal video signal composed of, for example, 8-bit red (R) video data, 8-bit green (G) video data, 8-bit blue (B) video data, a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal. The logic controller 62 generates driving control signals SA, SY, and SX in response to the internal video signal from the video processor 66. The address driver 63 processes the address signal SA among the driving control signals SA, SY, and SX output from the logic controller 62 to generate a display data signal and applies the display data signal to address electrode lines. The X-driver 64 processes the X-driving control signal SX among the driving control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to X-electrode lines. The Y-driver 65 processes the Y-driving control signal SY among the driving control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to Y-electrode lines.
An address-display separation driving scheme can be used in the plasma display panel 1 as described in U.S. Pat. No. 5,541,618, which is hereby incorporated by reference in its entirety. In the address-display separation driving scheme, the address period and the display-sustain period are separated in terms of time domain in each subfield included in a unit frame. Accordingly, during the address period, each XY-electrode line pair is held in standby after being addressed until all of the other XY-electrode line pairs are addressed. Such a standby period makes the wall charges in each display cell disordered. As a result, in the display-sustain period starting from an end point of the address period, accuracy of display-sustain discharge is decreased.
Referring to FIG. 4, the Y-driver (65 of FIG. 3) of a typical driving apparatus using the address-display separation driving scheme includes a reset/sustain circuit RSC, a scan driving circuit AC, and a switching output circuit SIC. The reset/sustain circuit RSC generates driving signals ORS to be applied to the Y-electrode lines Y1 through Yn during the reset period and the display-sustain period. The scan driving circuit AC generates driving signals to be applied to the Y-electrode lines Y1 through Yn during the address period. The switching output circuit SIC includes upper transistors YU1 through YUn and lower transistors YL1 through YLn. Common output lines of the respective upper and lower transistor pairs are connected to the Y-electrode lines Y1 through Yn, respectively. An operation of the Y-driver shown in FIG. 4 will be described with reference to FIGS. 1 and 4.
During the reset period and the display-sustain period, the driving signals ORS generated by the reset/sustain circuit RSC are applied to the Y-electrode lines Y1 through Yn of the plasma display panel 1 via a node A of the scan driving circuit AC and the lower transistors YL1 through YLn of the switching output circuit SIC. In this situation, first through fourth high power transistors SSC1, SSC2, SSP, and SSCL of the scan driving circuit AC are all turned off. The driving signals ORS may be applied to the Y-electrode lines Y1 through Yn of the plasma display panel 1 via the node A of the scan driving circuit AC, the third high power transistor SSP, and the upper transistors YU1 through YUn of the switching output circuit SIC. In this situation, the high power transistors SSC1, SSC2, and SSCL other than the third high power transistor SSP are turned off.
During the address period, the high power transistors SSC1, SSC2, and SSCL other than the third high power transistor SSP of the scan driving circuit AC are turned on. Then, a scan bias voltage VSCAN is applied to the upper transistors YU1 through YUn of the switching output circuit SIC via the first and second high power transistors SSC1 and SSC2. In addition, a ground voltage is applied to the lower transistors YL1 through YLn of the switching output circuit SIC via the fourth high power transistor SSCL. Then, a lower transistor connected to a Y-electrode line to be scanned is turned on, and an upper transistor connected to the Y-electrode line to be scanned is turned off. In addition, lower transistors connected to the other Y-electrodes not to be scanned are turned off, and upper transistors connected thereto are turned on. As a result, a scan ground voltage is applied to the Y-electrode line to be scanned, and the scan bias voltage VSCAN is applied to the other Y-electrode lines not to be scanned.
The following description concerns current paths respectively when the scan ground voltage is applied to the Y-electrode line to be scanned, when the display data signal is applied to the address electrode lines AR1 through ABm, when the application of the display data signal to the address electrode lines AR1 through ABm is terminated, and when the application of the scan ground voltage to the Y-electrode line being scanned is terminated, during the address period.
When the scan ground voltage is applied to the Y-electrode line to be scanned, a current flows from display cells (i.e., electric capacitors) connected to the Y-electrode line to be scanned to a ground terminal via a lower transistor of the switching output circuit SIC and the fourth high power transistor SSCL of the scan driving circuit AC.
When the display data signal is applied to the address electrode lines AR1 through ABm, a discharge current flows from address electrode lines to which a selection voltage is applied to the Y-electrode line which is being scanned, and a current flows to a terminal of the scan bias voltage VSCAN via the other Y-electrode lines which are not being scanned, upper transistors of the switching output circuit SIC, and the first and second high power transistors SSC1 and SSC2 of the scan driving circuit AC.
When the application of the display data signal to the address electrode lines AR1 through ABm is terminated, a current flows from the terminal of the scan bias voltage VSCAN to the address electrode lines AR1 through ABm via the first and second high power transistors SSC1 and SSC2 of the scan driving circuit AC, upper transistors of the switching output circuit SIC, and Y-electrode lines.
When the application of the scan ground voltage to the Y-electrode line being scanned is terminated, a current flows from the terminal of the scan bias voltage VSCAN to the display cells via the first and second high power transistors SSC1 and SSC2 of the scan driving circuit AC, upper transistors of the switching output circuit SIC, and Y-electrode lines.
Accordingly, it can be inferred that a high power transistor for switching needs to be connected between an upper common line of the upper transistors YU1 through YUn of the switching output circuit SIC and the terminal of the scan bias voltage VSCAN. When only a single high power transistor SSC1 or SSC2 is connected, the following problems occur.
When only the second high power transistor SSC2 is connected, during the reset period and the display-sustain period, the driving signals ORS of the reset/sustain circuit RSC are applied to the terminal of the scan bias voltage VSCAN via an internal diode of the second high power transistor SSC2, and thus a current flows. As a result, a driving operation during the reset period and the display-sustain period is instable and requires high power consumption.
When only the first high power transistor SSC1 is connected, an unexpected over-shoot pulse of the terminal of the scan bias voltage VSCAN may be applied to all of the upper transistors YU1 through YUn of the switching output circuit SIC via an internal diode of the first high power transistor SSC1. As a result, a driving operation during all of the periods is instable.
Consequently, two high power transistors SSC1 and SSC2 are needed.
In the meantime, when the third high power transistor SSP is not connected and thus the upper common line of the upper transistors YU1 through YUn is merely disconnected with a lower common power line of the lower transistors YL1 through YLn, during the reset period and the display-sustain period, the driving signals ORS of the reset/sustain circuit RSC are applied to all of the Y-electrode lines Y1 through Yn via all of the lower transistors YL1 through YLn of the switching output circuit SIC and also applied to the first high power transistor SSC1 via internal diodes of the upper transistors YU1 through YUn and the second high power transistor SSC2 of the scan driving circuit AC. As a result, the performance and the life span of the first high power transistor SSC1 are decreased. However, when the third high power transistor SSP is connected, a voltage is dropped down by a predetermined level by the third high power transistor SSP so that a voltage applied to the first high power transistor SSC1 can be decreased.
In the typical driving apparatus using a Y-driver having the above-described structure, even when all of the lower transistors YL1 through YLn of the switching output circuit SIC are turned off, the driving signals ORS of the reset/sustain circuit RSC are applied to all of the Y-electrode lines Y1 through Yn via the lower common power line and the internal diodes of the upper transistors YU1 through YUn. Accordingly, in a typical address-display separation driving apparatus using the above-described Y-driver, the address period must be separated from the display-sustain period in terms of time domain in each subfield included in a unit frame. In this situation, during the address period, each XY-electrode line pair is necessarily held in standby after being addressed until all of the other XY-electrode lines are addressed. Due to an existence of the standby duration after addressing, a state of wall charges in each display cell is disordered. As a result, in the display-sustain period starting from an end point of the address period, accuracy of display-sustain discharge decreases.